1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming spacer adjacent to contact etch stop layer (CESL).
2. Description of the Prior Art
In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
However, in current fabrication of high-k metal transistor, particularly during the stage when part of the metal gate is removed and a protective hard mask is formed on the metal gate, the design of current protective hard mask is no longer effective in protecting metal gate from damages. Hence, how to resolve this issue has become an important task in this field.